Semiconductor devices, such as RFID devices, solar cells, lasers, photodetectors, optical modulators, light emitting diodes, and the like, represent important classes of devices. These semiconductor devices are enabling devices for applications across a broad range of areas, including integrated circuit manufacture and test, RFID labeling, medicine, optical telecommunications, military, analytical, astronomy, and energy conversion, to name just a few.
Vertical arrays of nanopillars, nanowires or nanocones have been sought after for use in many of these applications. For example, vertical silicon nanopillars with aspect ratios less than 5 have been used as nano-imprint mask masters. In addition, vertical nanowire arrays of larger aspect ratios have been exploited in solar cells structures and vertical field effect transistors.
With regard to optoelectronic semiconductor devices, prior-art studies have demonstrated that a tapered geometry in vertical nanocone arrays can reduce light reflection via refractive index matching. Such structures are also suitable for use as scanning probe tips.
Nanowire-based devices have also shown potential to improve battery performance. Silicon and germanium nanowires have been used as negative electrodes in lithium-ion batteries.
For many of prior-art applications, it is important to precisely control diameter, spacing and shape of the vertical nanostructures. It is also important that the nanostructure arrays are fabricated over a large area with high throughput and low cost. Several prior-art methods have been developed to fabricate such arrays.
Nanowire arrays have been synthesized by vapor liquid solid growth with diameter control. Obtaining nanowires with small spacing between them has been challenging, however, due the propensity for the metal-catalyst particles to merge at growth temperatures.
Alternatively, nanowires have been made by solution chemistry. Unfortunately, the control of spacing and diameter of nanowires fabricated using this method is limited.
Electron-beam lithography and etching have been used in combination to form features smaller than 10 nm. The cost this approach is prohibitive, however. In addition, the throughput is low.
Photolithography is a tempting method, although the cost is too high for many applications.
In order to exploit the advantages afforded by substrates comprising arrays of nanometer-scale projections, an inexpensive, high-throughput fabrication method that provides good control over the physical characteristics of the projections would represent a significant advance in the state-of-the-art.